[Semiconductor Wafer Test Probe Card]

* Memory Application: NAND Flash, DRAM

* Non-memory Application: SoC (Vertical), CIS (MEMS), DDI, DC Parametric etc.

A probe card is an interface between an electronic test system and a semiconductor wafer. Its purpose is to provide an electrical pathway between a test system and the circuits in a wafer, thereby permitting the testing and validation of the circuits at the wafer level, usually before they are diced and packaged.

1. NAND FLASH & DRAM Testing Probe Card
As the use of AI (artificial intelligence) expands, demand for next-generation memory products is increasing in data centers and AI servers. Next-generation memory products feature high capacity, high-speed computation, high performance, and low power consumption.

FLASH memory can retain data regardless of power on/off and is applied to USBs, SD cards, SSDs, etc.

The number of layers in 3D NAND is expected to increase from the current 200-300 layers to 500-600 layers within the next few years. Consequently, hybrid bonding technology is anticipated to be applied and expanded in 3D NAND, similar to DRAM. This brings challenges such as cell current management, new equipment process development, stress/warpage compensation processes, defect-free hybrid bonding technology, and XY cell miniaturization.

KI is collaborating with the world's leading chipmakers to develop solutions for the increasing number of chip I/Os, driven by the trend toward higher integration and faster speeds in NAND Flash chips.

2. System on Chip (SoC) Testing Probe Card
As data traffic generated from various devices continue to surge, the demand for faster and more efficient logic chips solution is increasing. The logic chips are being packaged in smaller form factors, utilizing flip chips ball grid array (FC-BGA), wafer-level packaging (WLP), system in package (SiP) and system on chips (SoC) for higher integration.

To keep pace with these advances, semiconductor manufacturers are facing to reduce the total cost of testing. The purpose of testing cost reduction is to eliminate unnecessary packaging of defectives, by conducting test at the wafer-level.

Because the test active area for FC-BGA and SoC applications need to be expanded, while maintaining electrical and mechanical performance such as current carrying capacity, fine pitch, pin force, the probe card design complexity increases as well.

To address these challenges, it is necessary to adapt vertical probe card solution.

KI's wafer probe cards deliver precision and efficiency to address evolving test challenges and boast a long life span.